1. Field of the Invention
The present invention is generally in the field of semiconductors. More particularly, the present invention is in the field of capacitor fabrication in semiconductor dies.
2. Background Art
Integrated capacitors comprise a fundamental building block of integrated analog and mixed signal circuits fabricated on semiconductor dies. Metal-insulator-metal (MIM) type capacitors are particularly desired in the field because, for example, they exhibit a substantially linear response to an applied voltage and because they are relatively insensitive to temperature fluctuations. Conventional integrated MIM capacitors are typically fabricated during back end of the line (BEOL) processing because, historically, metal has not been a conventional constituent of other semiconductor device processing steps.
A conventional MIM capacitor can be fabricated, for example, by forming a dielectric layer for a MIM capacitor dielectric between metal layers for lower and upper MIM capacitor electrodes in the otherwise unused “vertical” space available over a semiconductor die during BEOL processing. However, forming the dielectric and metal layers during BEOL processing can require multiple process steps and masks, which can undesirably increase manufacturing cost.
In addition, BEOL processing significantly lags state-of-the-art size reduction techniques, and so as other design processes scale down, BEOL processing increasingly fails to produce detailed device structures as small as desired or as precisely as desired. As a result, BEOL fabricated MIM capacitors have relatively poor reliability, accuracy and density statistics.
Thus, there is a need to overcome the drawbacks and deficiencies in the art by providing an integrated capacitor that leverages high resolution processing techniques while minimizing the number of additional required processing steps.